# Cortex Check

> Lints one ARM Cortex-M firmware module (C, C++ or Rust) in the browser for the hazards that work under the debugger
> and fail in the field, each rule citing the section of the source skill it comes from, and works out a timing budget
> from the numbers given. Two metered runs then write the review, finding by finding, and the corrected module, which
> the page lints again. Built on the SkillSafe skill @sickn33/arm-cortex-expert, from sickn33/antigravity-awesome-skills
> (MIT). NVIC priority bits, clocks and rates are never guessed: they come from the form.

https://cortex-check.skillsafe.ai/

## What is free
- A lexer that blanks comments and string and char literals while keeping line numbers, brace matching for function bodies, and ISR detection: C/C++ *_IRQHandler and *_Handler names and functions passed to attachInterrupt or attachInterruptVector; Rust functions under #[interrupt] or #[exception].
- Fails: a blocking call inside an ISR (delays, prints, a polling HAL_UART_Transmit, the heap, a busy-wait), static mut in Rust, a DMA buffer without 32-byte alignment or with a size that is not a multiple of 32 on a Cortex-M7 with the D-cache on or unknown, BASEPRI on M0/M0+, an NVIC priority at or above 2^bits when the bits are given, SPISettings above 30 MHz on Teensy 4.x, more than 8 GPIOTE channels on nRF52.
- Warnings: a FreeRTOS queue, semaphore or notify call without the FromISR form in an ISR (a FreeRTOS API rule, not the skill's), a variable written in an ISR and read outside it without volatile or an atomic type, DMA on a cached M7 without cache maintenance or non-cacheable placement (and maintenance in the reverse order), a missing barrier on M7 (the "works with debug prints" symptom, or a clock enable followed by the peripheral's first access), a read-modify-write clear of a status register (write-1-to-clear), __disable_irq without saving PRIMASK, long critical sections, unaligned wide access on M0/M0+, Teensy EEPROM, CCM and FlexSPI use, SAADC without calibration, 5 V signals.
- Info: the NVIC bands (0-2 time-critical, 3-7 normal peripherals, 8+ background), equal priorities that cannot preempt, BASEPRI over PRIMASK, FPU lazy stacking in an ISR, HardFault handlers that do not capture the stacked frame, stack protection, SAMD and STM32 F7/H7 notes.
- The timing budget: ISR time, CPU load, the bytes per second (baud / 10 for 8N1, stated), the time to fill the buffer and the main loop's drain interval, each with its formula.
- Exports: the findings (.csv), the report (.md), the NVIC table (.csv) and everything (.json).

## The metered lanes
Two tasks on gpt-terra, metered per run, chosen by `task`. Text fields of the input: `task` (review or rewrite), `module` (the numbered source), `context`, `carry` (rewrite only: the carried review) and `facts` (the page's checks).
- `review` replies with `summary`, `findings` (id, where, why, fix - one per page fail and warn, in order, plus at most 4 extra- findings tied to a line), `priorities` (irq, current, proposed, why), `timing`, `hardware_tests` (at least 3) and `caveats`.
- `rewrite` replies with `filename`, `language`, `code` (the complete module), `changes` (id, what), `assumptions`, `test_plan` and `caveats`.
The page holds each reply to its facts: every page id and line in order, priorities only for the page's IRQs and inside the given bits, no new number in the timing sentence, no claim of having compiled or flashed anything, no link; and the rewrite's code is re-linted with the same context - no fail may remain or be introduced, and every ISR is kept.

## Links
- API tutorial: https://cortex-check.skillsafe.ai/api.html
- Source skill: https://skillsafe.ai/skill/@sickn33/arm-cortex-expert

An independent tool, not affiliated with or endorsed by Arm; Arm and Cortex are trademarks of Arm Limited.