For firmware that works under the debugger and fails in the field
Cortex CheckLint a Cortex-M driver for the hazards the bench hides - then the review and the corrected module.
Paste one module in C, C++ or Rust and say what it runs on. The browser blanks comments and strings, finds the functions and the ISRs, and checks for blocking calls in interrupts, shared data without volatile, static mut, DMA buffers that are unaligned on a cached M7, missing barriers, write-1-to-clear status bits, long or non-nesting critical sections and NVIC priorities - each rule citing the skill it comes from. Priority bits, clocks and rates are never guessed: they come from you.
The module free
Stays in your browser until you run a metered lane. Line numbers in the checks are this box's lines.
What it runs on free
Priority bits depend on the exact MCU: leave the box blank and the page will not range-check the priorities.
The timing budget free
What the page found free
Fails and warnings, in order
Since the saved scan
The module, line by line
NVIC priorities
Every check, area by area
The review metered
The price shows once the session is ready...
Sign inThe reply could not be read. It came back as:
Caveats
Caveats
The page's check of this reply
Saved checks
How it works - and what the page does not do
The lint runs only the skill's rules. Blocking calls (delays, prints, polling UART transmits, the heap, busy-waits) inside an ISR fail; a FreeRTOS queue, semaphore or notify call without the FromISR form is a warning, because that is a FreeRTOS API fact rather than the skill's. On a Cortex-M7 with the D-cache on or unknown, a DMA buffer must be 32-byte aligned with a size that is a multiple of 32, and the page looks for cache maintenance or a non-cacheable placement. Barriers, write-1-to-clear status bits, PRIMASK nesting, long critical sections, shared variables without volatile and the platform gotchas (Teensy 4.x, nRF52, SAMD, STM32 F7/H7) are warnings where the skill says to confirm in the reference manual.
The page never assumes a chip value: NVIC priority bits, clocks and byte rates come from the form, and the timing budget is arithmetic on your numbers. It reads the module as text - it does not compile it, follow calls into other files or see the linker map, so a buffer placed in non-cacheable memory by the linker script is not visible to it. Confirm every value against the datasheet and reference manual before flashing or energizing connected hardware.